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Disambiguation of "Tahoori, Mehdi Baradaran"

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Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design.

, , , and . ACM Trans. Design Autom. Electr. Syst., 24 (4): 41:1-41:25 (2019)

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Mehdi Tavakoli University of Stuttgart

 

Other publications of authors with the same name

Aging-Aware Design of Microprocessor Instruction Pipelines., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (5): 704-716 (2014)Stress-aware P/G TSV planning in 3D-ICs., , , and . ASP-DAC, page 94-99. IEEE, (2015)Fault injection acceleration by architectural importance sampling., , , and . CODES+ISSS, page 212-219. IEEE, (2015)High-level aging estimation for FPGA-mapped designs., and . FPL, page 284-291. IEEE, (2012)Towards dark silicon era in FPGAs using complementary hard logic design., , , , and . FPL, page 1-6. IEEE, (2014)Aging-aware timing analysis considering combined effects of NBTI and PBTI., , and . ISQED, page 53-59. IEEE, (2013)Chip-level modeling and analysis of electrical masking of soft errors., , , and . VTS, page 1-6. IEEE Computer Society, (2013)A mapping algorithm for defect-tolerance of reconfigurable nano-architectures.. ICCAD, page 668-672. IEEE Computer Society, (2005)Defects and Faults in Quantum Cellular Automata at Nano Scale., , , and . VTS, page 291-296. IEEE Computer Society, (2004)Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames., , , and . IEEE Trans. VLSI Syst., 24 (3): 932-943 (2016)