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Disambiguation of "Mudge, Trevor N."

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Architecting an LTE base station with graphics processing units.

, , , , , , and . SiPS, page 219-224. IEEE, (2013)

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Dr. Quynh Ngo University of Stuttgart

Dataset for NMF-based Analysis of Mobile Eye-Tracking Data, , , and . Dataset, (2024)Related to: Daniel Klötzl, Tim Krake, Frank Heyen, Michael Becher, Maurice Koch, Daniel Weiskopf, and Kuno Kurzhals. 2024. NMF-Based Analysis of Mobile Eye-Tracking Data. In 2024 Symposium on Eye Tracking Research and Applications (ETRA ’24), June 4-7, 2024, Glasgow, United Kingdom. ACM, New York, NY, USA, 9 pages. doi: 10.1145/3649902.3653518.

Jan-Philipp Negel

Thin-disk multipass amplifier for fs pulses delivering 400 W of average and 2.0 GW of peak power for linear polarization as well as 235 W and 1.2 GW for radial polarization, , , , , , , and . Applied Physics. B, Lasers and optics, 123 (5): 156 (2017)

Univ. -Prof. Dr. -Ing. Wolfgang Nowak University of Stuttgart

Optimized Predictive Coverage by Averaging Time-Windowed Bayesian Distributions, , , and . Water resources research, 60 (5): e2022WR033280 (2024)

Univ. -Prof. Ph. D. Mathias Niepert University of Stuttgart

Learning Disentangled Discrete Representations, , , and . Machine Learning and Knowledge Discovery in Databases : Research Track, volume 4 : Research Track of Lecture notes in computer science. Lecture notes in artificial intelligence, page 593-609. Cham, Springer, (2023)

Dr. Philipp Ninz University of Stuttgart

Laser Induced Selective Metallization of 3D Ceramic Interconnect Devices, , , , , , , and . 2018 13th International Congress Molded Interconnect Devices (MID), IEEE, (2018)
 

Other publications of authors with the same name

PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis., , and . ISPASS, page 32-41. IEEE Computer Society, (2005)Architecture of a Hypercube Supercomputer., , and . ICPP, page 653-660. IEEE Computer Society Press, (1986)PEPSC: A Power-Efficient Processor for Scientific Computing., , , and . PACT, page 101-110. IEEE Computer Society, (2011)Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores., , and . ICSAMOS, page 191-198. IEEE, (2014)Sirius Implications for Future Warehouse-Scale Computers., , , , , , , , , and 1 other author(s). IEEE Micro, 36 (3): 42-53 (2016)Impact of Future Technologies on Architecture., , , , , and . IEEE Micro, 36 (4): 48-56 (2016)ChipLock: support for secure microarchitectures., , and . SIGARCH Computer Architecture News, 33 (1): 134-143 (2005)The limits of instruction level parallelism in SPEC95 applications., , , and . SIGARCH Computer Architecture News, 27 (1): 31-34 (1999)Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation., , , , , , , and . IEEE Micro, 24 (6): 10-20 (2004)Quantitative analysis and optimization techniques for on-chip cache leakage power., , and . IEEE Trans. VLSI Syst., 13 (10): 1147-1156 (2005)