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Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness., , , , and . Microelectronics Reliability, 51 (5): 919-924 (2011)A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion., , , and . IEEE Trans. on Circuits and Systems, 57-I (9): 2404-2412 (2010)Analysis of the QAC IR-UWB Receiver for Low Energy, Low Data-Rate Communication., and . IEEE Trans. on Circuits and Systems, 55-I (8): 2423-2432 (2008)Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs., , , and . Signal Processing Systems, 52 (2): 193-210 (2008)Robust digital design in organic electronics by dual-gate technology., , , , , , and . ISSCC, page 140-141. IEEE, (2010)SC1: Circuit design in advanced CMOS technologies: How to design with lower supply voltages.. ISSCC, page 1-2. IEEE, (2015)Bidirectional communication in an HF hybrid organic/solution-processed metal-oxide RFID tag., , , , , , , , , and 4 other author(s). ISSCC, page 312-314. IEEE, (2012)A method for using sub-Nyquist sampling for ultra low-power positioning systems., , and . SiPS, page 100-105. IEEE, (2013)A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context., , , , and . DATE, page 929-933. IEEE, (2009)Impact of interconnect multiple-patterning variability on SRAMs., , , , , , , , and . DATE, page 609-612. ACM, (2015)