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Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM.

P. Poliakov, A. Anchlia, M. Bardon, B. Rooseleer, B. Wachter, N. Collaert, K. van der Zanden, W. Dehaene, D. Verkest, and M. Miranda. IEEE Trans. on Circuits and Systems, 57-II (3): 183-187 (2010)

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Rahul Barthwal University of Stuttgart

Lukas Bartholomäus University of Stuttgart

Dr. rer. nat. Simon Barth University of Stuttgart

Aneesh Barthakur University of Stuttgart

Alexander Bartler University of Stuttgart

Other publications of authors with the same name

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps.W. Guo, G. der Plas, A. Ivankovic, G. Eneman, V. Cherman, B. Wachter, A. Mercha, M. Gonzalez, Y. Civale, A. Redolfi and 9 other author(s). ICICDT, page 1-4. IEEE, (2012)A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards.E. Marinissen, F. Fodor, B. Wachter, J. Kiesewetter, E. Hill, and K. Smith. ITC-Asia, page 144-149. IEEE, (2017)Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.G. der Plas, P. Limaye, I. Loi, A. Mercha, H. Oprins, C. Torregiani, S. Thijs, D. Linten, M. Stucchi, G. Katti and 27 other author(s). J. Solid-State Circuits, 46 (1): 293-307 (2011)Vesuvius-3D: A 3D-DfT demonstrator.E. Marinissen, B. Wachter, S. O'Loughlin, S. Deutsch, C. Papameletis, and T. Burgherr. ITC, page 1-10. IEEE Computer Society, (2014)Automated testing of bare die-to-die stacks.E. Marinissen, B. Wachter, T. Wang, J. Fiedler, J. Kiesewetter, and K. Stoll. ITC, page 1-10. IEEE, (2015)Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM.P. Poliakov, A. Anchlia, M. Bardon, B. Rooseleer, B. Wachter, N. Collaert, K. van der Zanden, W. Dehaene, D. Verkest, and M. Miranda. IEEE Trans. on Circuits and Systems, 57-II (3): 183-187 (2010)Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface.E. Marinissen, B. Wachter, K. Smith, J. Kiesewetter, M. Taouil, and S. Hamdioui. ITC, page 1-10. IEEE Computer Society, (2014)Design issues and considerations for low-cost 3D TSV IC technology.G. der Plas, P. Limaye, A. Mercha, H. Oprins, C. Torregiani, S. Thijs, D. Linten, M. Stucchi, G. Katti, D. Velenis and 24 other author(s). ISSCC, page 148-149. IEEE, (2010)

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Disambiguation of "Wachter, Bart De"

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Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM.

Please choose a person to relate this publication to

Rahul Barthwal University of Stuttgart

Lukas Bartholomäus University of Stuttgart

Dr. rer. nat. Simon Barth University of Stuttgart

Aneesh Barthakur University of Stuttgart

Alexander Bartler University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Wachter, Bart De"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM.

Please choose a person to relate this publication to

Rahul Barthwal University of Stuttgart

Lukas Bartholomäus University of Stuttgart

Dr. rer. nat. Simon Barth University of Stuttgart

Aneesh Barthakur University of Stuttgart

Alexander Bartler University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM.