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A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication.

, , , , , , , and . CICC, page 451-454. IEEE, (2007)

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A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication., , , , , , , and . CICC, page 451-454. IEEE, (2007)Wireless Implant Communications for Biomedical Monitoring Sensor Network., , , , and . ISCAS, page 809-812. IEEE, (2007)Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications., , , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 446-455. Springer, (2005)42% power savings through glitch-reducing clocking strategy in a hearing aid application., , , , and . ISCAS, IEEE, (2006)Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers., , , , and . IEEE Trans. VLSI Syst., 16 (7): 830-836 (2008)Two-phase resonant clocking for ultra-low-power hearing aid applications., , , , and . DATE, page 73-78. European Design and Automation Association, Leuven, Belgium, (2006)Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm., , , , , , , , and . DAC, page 558-561. ACM, (2006)