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Disambiguation of "Hu, Jiang"

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A dual-level adaptive supply voltage system for variation resilience.

, , and . ISQED, page 38-43. IEEE, (2010)

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Chenming Jiang University of Stuttgart

Huimin Hu University of Stuttgart

Yang Hu University of Stuttgart

Zhiming Hu University of Stuttgart

Adrian Humboldt University of Stuttgart

A ProTide of AZT Shows Activity Against Human Papillomaviruses, , , , and . ChemMedChem, 19 (8): e202300661 (2024)
 

Other publications of authors with the same name

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm., , , , and . Integration, 41 (3): 426-438 (2008)Boostable Repeater Design for Variation Resilience in VLSI Interconnects., and . IEEE Trans. VLSI Syst., 21 (9): 1619-1631 (2013)Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations., , and . IEEE Trans. VLSI Syst., 17 (3): 439-443 (2009)Low Power Gated Clock Tree Driven Placement., , , and . IEICE Transactions, 91-A (2): 595-603 (2008)STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip., , , and . NOCS, page 176-177. IEEE, (2014)Guest Editorial Special Section on the 2011 International Symposium on Physical Design., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (2): 165-166 (2012)Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (10): 1558-1571 (2012)Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding., , , , and . ISQED, page 627-632. IEEE Computer Society, (2008)Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders., , and . ISQED, page 749-754. IEEE Computer Society, (2007)Efficient Model Update for General Link-Insertion Networks., , and . ISQED, page 43-50. IEEE Computer Society, (2006)