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Guest Editors' Introduction: Exploring Synergies for Design Verification., and . IEEE Design & Test of Computers, 21 (6): 461-463 (2004)Theory of safe replacements for sequential circuits., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (2): 249-265 (2001)Automatic Vector Generation Using Constraints and Biasing., , , , and . J. Electronic Testing, 16 (1-2): 107-120 (2000)A Computation Theory and Implementation of Sequential Hardware Equivalence.. CAV (DIMACS/AMS volume), volume 3 of DIMACS Series in Discrete Mathematics and Theoretical Computer Science, page 293-320. DIMACS/AMS, (1990)Commercial Design Verification: Methodology and Tools., , , , , , , , , and . ITC, page 839-848. IEEE Computer Society, (1996)Memory Modeling in ESL-RTL Equivalence Checking., , and . DAC, page 205-209. IEEE, (2007)A Framework for Constrained Functional Verification., , , and . ICCAD, page 142-145. IEEE Computer Society / ACM, (2003)Simplifying Boolean constraint solving for random simulation-vector generation., , , and . ICCAD, page 123-127. ACM / IEEE Computer Society, (2002)Minimum Length Synchronizing Sequences of Finite State Machine., , and . DAC, page 463-468. ACM Press, (1993)Guest Editors' Introduction: The True State of the Art of ESL Design., , and . IEEE Design & Test of Computers, 23 (5): 335-337 (2006)