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Applied Boolean Equivalence Verification and RTL Static Sign-Off.. IEEE Design & Test of Computers, 18 (4): 6-15 (2001)2018 FPGA Functional Verification Trends.. MTV, page 40-45. IEEE, (2018)Bridging pre-silicon verification and post-silicon validation., , , , , , , , , and . DAC, page 94-95. ACM, (2010)Functional test selection based on unsupervised support vector analysis., , , and . DAC, page 262-267. ACM, (2008)Pain, Possibilities, and Prescriptions Industry Trends in Advanced Functional Verification.. Haifa Verification Conference, volume 6405 of Lecture Notes in Computer Science, page 2. Springer, (2009)Formal verification methods: getting around the brick wall., , , , , , , , and . DAC, page 576-577. ACM, (2002)Why the design productivity gap never happened.. ICCAD, page 581-584. IEEE, (2013)Panel: Unified approach leading to a seamlessly evolving test bench for all phases of a multi-core design, validation and production test., , , , and . HLDVT, page 167-168. IEEE Computer Society, (2007)Panel: Driving the intelligent testbanch: are we there yet?. HLDVT, page 188. IEEE Computer Society, (2004)The Chip is Ready. Am I done? On-chip Verification using Assertion Processors., , , , and . VLSI-SOC, page 111-. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)