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Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm.

, , , and . IEICE Transactions, 88-A (12): 3412-3420 (2005)

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An analytical model of the overshooting effect for multiple-input gates in nanometer technologies., , , , and . ISCAS, page 1712-1715. IEEE, (2013)Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills., , , , , , , and . ISQED, page 586-591. IEEE Computer Society, (2005)An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs., , , , , , and . ISQED, page 519-523. IEEE, (2015)A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect., , , , , and . IEICE Transactions, 94-A (5): 1201-1209 (2011)Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability., , and . IEICE Transactions, 92-A (12): 2962-2970 (2009)DEPOGIT: dense power-ground interconnect architecture for physical design integrity., , , and . ASP-DAC, page 517-522. IEEE Computer Society, (2004)Modeling the Overshooting Effect of Multi-Input gate in Nanometer Technologies., , , , and . Journal of Circuits, Systems, and Computers, (2012)Prevention in a Chip of EMI Noise Caused by X'tal Oscillator., , and . IEICE Transactions, 91-A (4): 1077-1083 (2008)Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance., , , , , , , and . IEICE Transactions, 88-A (12): 3453-3462 (2005)Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays., , , , , , and . IEICE Transactions, 89-A (4): 856-864 (2006)