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Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults.

Y. Peng, D. Kwai, Y. Chou, and C. Wu. IEEE Trans. VLSI Syst., 22 (2): 207-219 (2014)

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Michel Choudalakis University of Stuttgart

Roland Falk University of Stuttgart

Daniel Fahse University of Stuttgart

Jan Falter University of Stuttgart

Rouven Fauser University of Stuttgart

Other publications of authors with the same name

Hierarchical Test Integration Methodology for 3-D ICs.C. Chou, J. Li, Y. Yu, C. Lo, D. Kwai, and Y. Chou. IEEE Design & Test, 32 (4): 59-70 (2015)A hybrid ECC and redundancy technique for reducing refresh power of DRAMs.Y. You, C. Hou, L. Chang, J. Li, C. Lo, D. Kwai, Y. Chou, and C. Wu. VTS, page 1-6. IEEE Computer Society, (2013)3D-IC BISR for stacked memories using cross-die spares.C. Chi, Y. Chou, D. Kwai, Y. Hsiao, C. Wu, Y. Hsing, L. Denq, and T. Lin. VLSI-DAT, page 1-4. IEEE, (2012)A hybrid built-in self-test scheme for DRAMs.C. Yang, J. Li, Y. Yu, K. Wu, C. Lo, C. Chen, J. Lai, D. Kwai, and Y. Chou. VLSI-DAT, page 1-4. IEEE, (2015)CAD reference flow for 3D via-last integrated circuits.C. Lin, D. Kwai, Y. Chou, T. Chen, and W. Wu. ASP-DAC, page 187-192. IEEE, (2010)General Modular Multiplication by Block Multiplication and Table Lookup.C. Wu, and Y. Chou. ISCAS, page 295-298. IEEE, (1994)A self-testing and calibration method for embedded successive approximation register ADC.X. Huang, P. Kang, H. Chang, J. Huang, Y. Chou, Y. Lee, D. Kwai, and C. Wu. ASP-DAC, page 713-718. IEEE, (2011)A built-in self-repair scheme for DRAMs with spare rows, columns, and bits.C. Hou, Y. Chen, J. Li, C. Lo, D. Kwai, and Y. Chou. ITC, page 1-7. IEEE, (2016)On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC.S. Fang, C. Lin, W. Liao, C. Huang, L. Chen, H. Chen, I. Lee, D. Kwai, and Y. Chou. ISVLSI, page 459-464. IEEE Computer Society, (2017)SRAM delay fault modeling and test algorithm development.R. Huang, Y. Lai, Y. Chou, and C. Wu. ASP-DAC, page 104-109. IEEE Computer Society, (2004)

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Disambiguation of "Chou, Yung-Fa"

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Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults.

Please choose a person to relate this publication to

Michel Choudalakis University of Stuttgart

Roland Falk University of Stuttgart

Daniel Fahse University of Stuttgart

Jan Falter University of Stuttgart

Rouven Fauser University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Chou, Yung-Fa"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults.

Please choose a person to relate this publication to

Michel Choudalakis University of Stuttgart

Roland Falk University of Stuttgart

Daniel Fahse University of Stuttgart

Jan Falter University of Stuttgart

Rouven Fauser University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults.