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Disambiguation of "Leupers, Rainer"

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Application-aware spinlock control using a hardware scheduler in MPSoC platforms.

, , , , , , and . ISSoC, page 1-6. IEEE, (2012)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

apl. Prof. Dr. Rainer Bäuerle University of Stuttgart

Rainer Goutrié University of Stuttgart

Dr. Rainer Stöhr University of Stuttgart

Rainer Kuhn University of Stuttgart

Rainer Valek University of Stuttgart

 

Other publications of authors with the same name

Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis., , , , , , and . IJERTCS, 2 (3): 1-20 (2011)A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding., , , , and . IEEE Trans. on Circuits and Systems, 57-II (9): 706-710 (2010)Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths., and . Design Autom. for Emb. Sys., 4 (2-3): 119-165 (1999)Retargetable compiler technology for embedded systems - tools and applications., and . Kluwer, (2001)Integrated system-level modeling of network-on-chip enabled multi-processor platforms., , and . Kluwer, (2006)Optimized buffer allocation in multicore platforms., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Register-Constrained Address Computation in DSP Programs., , and . DATE, page 929-930. IEEE Computer Society, (1998)An integrated open framework for heterogeneous MPSoC design space exploration., , , , , and . DATE, page 1145-1150. European Design and Automation Association, Leuven, Belgium, (2006)Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms., , , , , , , and . DATE, page 753-758. IEEE, (2010)Extraction of Kahn Process Networks from While Loops in Embedded Software., , , , and . HPCC/CSS/ICESS, page 1078-1085. IEEE, (2015)