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Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths., and . Design Autom. for Emb. Sys., 4 (2-3): 119-165 (1999)Integrated system-level modeling of network-on-chip enabled multi-processor platforms., , and . Kluwer, (2006)Optimized buffer allocation in multicore platforms., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms., , , , , , , and . DATE, page 753-758. IEEE, (2010)Extraction of Kahn Process Networks from While Loops in Embedded Software., , , , and . HPCC/CSS/ICESS, page 1078-1085. IEEE, (2015)Register-Constrained Address Computation in DSP Programs., , and . DATE, page 929-930. IEEE Computer Society, (1998)An integrated open framework for heterogeneous MPSoC design space exploration., , , , , and . DATE, page 1145-1150. European Design and Automation Association, Leuven, Belgium, (2006)Split-cost communication model for improved MPSoC application mapping., , , , and . ISSoC, page 1-8. IEEE, (2013)Trends in embedded software synthesis., , and . ICSAMOS, page 347-354. IEEE, (2011)Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis., , , , , , and . IJERTCS, 2 (3): 1-20 (2011)