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Integrated system-level modeling of network-on-chip enabled multi-processor platforms.

, , and . Kluwer, (2006)

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OCP TLM for Architectural Modelling., and . FDL, page 225-244. ECSI, (2005)A framework for fast hardware-software co-simulation., , and . DATE, page 760-765. IEEE Computer Society, (2001)A modular simulation framework for architectural exploration of on-chip interconnection networks., , , , , , and . CODES+ISSS, page 7-12. ACM, (2003)Integrated system-level modeling of network-on-chip enabled multi-processor platforms., , and . Kluwer, (2006)Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization., , , and . ASAP, page 161-171. IEEE Computer Society, (2003)A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform., , , , , , and . DATE, page 1256-1263. IEEE Computer Society, (2004)A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms., , , , , , and . DATE, page 876-881. IEEE Computer Society, (2005)ESL hand-off: fact or EDA fiction?, , , , , , , , and . DAC, page 310-312. ACM, (2008)Heterogeneous MP-SoC: the solution to energy-efficient signal processing., and . DAC, page 686-691. ACM, (2004)From ESL 2010 to ESL 2015., , , , , and . CODES+ISSS, page 61-62. ACM, (2010)