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Reliability challenges for barrier/liner system in high aspect ratio through silicon vias., , , , , , , , , and . Microelectronics Reliability, 54 (9-10): 1949-1952 (2014)Analysis of microbump induced stress effects in 3D stacked IC technologies., , , , , , , , , and 9 other author(s). 3DIC, page 1-5. IEEE, (2011)3D stacking using Cu-Cu direct bonding., , , , , , , , and . 3DIC, page 1-4. IEEE, (2011)In-line metrology and inspection for process control during 3D stacking of IC's., , , , , , , and . 3DIC, page 1-4. IEEE, (2011)Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics., , , , , and . 3DIC, page TS7.2.1-TS7.2.4. IEEE, (2015)Extreme wafer thinning optimization for via-last applications., , , , , , , , , and 3 other author(s). 3DIC, page 1-5. IEEE, (2016)3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps., , , , , , , , , and 9 other author(s). ICICDT, page 1-4. IEEE, (2012)Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding., , , , , , , , , and 6 other author(s). 3DIC, page 1-4. IEEE, (2011)TSV process-induced MOS reliability degradation., , , , , , and . IRPS, page 5. IEEE, (2018)