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Disambiguation of "Vasudevan, Shobha"

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Automatic Generation of System Level Assertions from Transaction Level Models.

, and . J. Electronic Testing, 29 (5): 669-684 (2013)

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Other publications of authors with the same name

Automatic Generation of System Level Assertions from Transaction Level Models., and . J. Electronic Testing, 29 (5): 669-684 (2013)Mining Hardware Assertions With Guidance From Static Analysis., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (6): 952-965 (2013)A Technique for Test Coverage Closure Using GoldMine., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (5): 790-803 (2012)Formal Probabilistic Timing Verification in RTL., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (5): 788-801 (2013)Improved verification of hardware designs through antecedent conditioned slicing., , and . STTT, 9 (1): 89-101 (2007)Using automatically generated invariants for regression testing and bug localization., , , and . ASE, page 634-639. IEEE, (2013)Diagnosing root causes of system level performance violations., , , and . ICCAD, page 295-302. IEEE, (2013)Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection., , , , and . ICCAD, page 1-8. IEEE, (2015)Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm., , and . DATE, page 21-26. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Automatic decomposition for sequential equivalence checking of system level and RTL descriptions., , , and . MEMOCODE, page 71-80. IEEE Computer Society, (2006)