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Power Aware Architecture Exploration for Field Programmable Gate Arrays.

, and . J. Low Power Electronics, 10 (3): 297-312 (2014)

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On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays., and . J. Low Power Electronics, 1 (2): 119-132 (2005)Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT., , , and . SoCC, page 357-360. IEEE, (2009)Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs)., , and . IEEE Trans. VLSI Syst., 19 (12): 2195-2208 (2011)Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture., and . FCCM, page 35-44. IEEE Computer Society, (2005)High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs., , , , and . FPL, page 1-4. IEEE, (2014)Effective FPGA debug for high-level synthesis generated circuits., and . FPL, page 1-8. IEEE, (2014)Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow., , and . ICCD, page 267-274. IEEE Computer Society, (2005)Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design., , , and . FPT, page 54-61. IEEE Computer Society, (2009)Placement and routing for FPGA architectures supporting wide shallow memories., and . FPT, page 154-161. IEEE, (2003)An FPGA architecture supporting dynamically controlled power gating., and . FPT, page 1-8. IEEE, (2010)