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Disambiguation of "Louri, Ahmed"

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LEAD: learning-enabled energy-aware dynamic voltage/frequency scaling in NoCs.

, , , and . DAC, page 82:1-82:6. ACM, (2018)

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Mohamed Osama Helal Ahmed University of Stuttgart

Ahmed Elkelesh University of Stuttgart

Dr. Marwan Abdou Ahmed University of Stuttgart

Ahmed Yassine Karoui University of Stuttgart

Ahmed El Hadi University of Stuttgart

 

Other publications of authors with the same name

Co-design of channel buffers and crossbar organizations in NoCs architectures., , , , and . ICCAD, page 219-226. IEEE Computer Society, (2011)A Parallel Architecture for Optical Computing., and . PPSC, page 414-418. SIAM, (1987)Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures., , , and . ASP-DAC, page 1-6. IEEE, (2009)A Compiler Directed Cache Coherence Scheme with Fast and Parallel Explicit Invalidation., and . ICPP (1), page 2-9. CRC Press, (1992)Dynamic error mitigation in NoCs using intelligent prediction techniques., , , and . MICRO, page 1-12. IEEE Computer Society, (2016)A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation., and . ISCA, page 428. ACM, (1992)LEAD: learning-enabled energy-aware dynamic voltage/frequency scaling in NoCs., , , and . DAC, page 82:1-82:6. ACM, (2018)Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture., , and . ANCS, page 47-56. ACM, (2007)Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures., , , and . IEEE Trans. Computers, 64 (12): 3555-3568 (2015)Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors., and . IEEE Micro, 25 (1): 41-49 (2005)