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Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator., , , , , , , , , and . DATE, page 78-83. IEEE, (2019)Including a stochastic model of aging in a reliability simulation flow., , , , , , , and . SMACD, page 1-4. IEEE, (2017)Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs., , , , , , , and . SMACD, page 1-9. IEEE, (2018)Reliability simulation for analog ICs: Goals, solutions, and challenges., , , , , , , and . Integration, (2016)CASE: A reliability simulation tool for analog ICs., , , , , , , and . SMACD, page 1-4. IEEE, (2017)Automated Massive RTN Characterization Using a Transistor Array Chip., , , , , , , , and . SMACD, page 29-32. IEEE, (2018)A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation., , , , , , , , and . SMACD, page 53-56. IEEE, (2018)A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs., , , , , , , and . ISCAS, page 1-4. IEEE, (2017)Layout-aware Pareto fronts of electronic circuits., , , and . ECCTD, page 345-348. IEEE, (2011)