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On-Chip Interconnection Architecture of the Tile Processor., , , , , , , , , and . IEEE Micro, 27 (5): 15-31 (2007)Selecting Spatiotemporal Patterns for Development of Parallel Applications., , and . IEEE Trans. Parallel Distrib. Syst., 23 (10): 1970-1982 (2012)Performance of Switch Blocking on Multithreaded Architectures., , , and . ICPP (1), page 275-284. CRC Press, (1994)Exploiting Two-Case Delivery for Fast Protected Messaging., , , , , , and . HPCA, page 231-242. IEEE Computer Society, (1998)Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture., , , and . HPCA, page 341-353. IEEE Computer Society, (2003)The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs., , , , , , , , , and 8 other author(s). IEEE Micro, 22 (2): 25-35 (2002)Architectural and implementation issues for multithreading (panel session I)., , , , , and . SIGARCH Computer Architecture News, 22 (1): 3-18 (1994)An Analytical Cache Model., , and . ACM Trans. Comput. Syst., 7 (2): 184-215 (1989)Factored operating systems (fos): the case for a scalable operating system for multicores., and . Operating Systems Review, 43 (2): 76-85 (2009)Tiled Multicore Processors., , , , , , , , , and 6 other author(s). Multicore Processors and Systems, Springer, (2009)