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Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.

M. Taylor, W. Lee, S. Amarasinghe, and A. Agarwal. HPCA, page 341-353. IEEE Computer Society, (2003)

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Nivedita Agarwal

Other publications of authors with the same name

Thousand-Core Chips Roundtable.D. Yeh, L. Peh, S. Borkar, J. Darringer, A. Agarwal, and W. mei W. Hwu. IEEE Design & Test of Computers, 25 (3): 272-278 (2008)Multigrain shared memory.D. Yeung, J. Kubiatowicz, and A. Agarwal. ACM Trans. Comput. Syst., 18 (2): 154-196 (2000)Anatomy of a Message in the Alewife Multiprocessor.J. Kubiatowicz, and A. Agarwal. International Conference on Supercomputing, page 195-206. ACM, (1993)An Evaluation of Directory Schemes for Cache Coherence.A. Agarwal, R. Simoni, J. Hennessy, and M. Horowitz. ISCA, page 280-289. IEEE Computer Society, (1988)Software-Extended Coherent Shared Memory: Performance and Cost.D. Chaiken, and A. Agarwal. ISCA, page 314-324. IEEE Computer Society, (1994)ATUM: A New Technique for Capturing Address Traces Using Microcode.A. Agarwal, R. Sites, and M. Horowitz. ISCA, page 119-127. IEEE Computer Society, (1986)Low-Cost Support for Fine-Grain Synchronization in Multiprocessors.D. Kranz, B. Lim, A. Agarwal, and D. Yeung. Multithreaded Computer Architecture, volume 281 of The Kluwer International Series in Engineering and Computer Science, Kluwer / Springer, (1994)ATAC: a 1000-core cache-coherent processor with on-chip optical network.G. Kurian, J. Miller, J. Psota, J. Eastep, J. Liu, J. Michel, L. Kimerling, and A. Agarwal. PACT, page 477-488. ACM, (2010)Application heartbeats: a generic interface for specifying program performance and goals in autonomous computing environments.H. Hoffmann, J. Eastep, M. Santambrogio, J. Miller, and A. Agarwal. ICAC, page 79-88. ACM, (2010)Compile-time Techniques for Processor Allocation in Macro Dataflow Graphs for Multiprocessors.G. Prasanna, and A. Agarwal. ICPP (2), page 279-283. CRC Press, (1992)

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Disambiguation of "Agarwal, Anant"

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Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.

Please choose a person to relate this publication to

Nivedita Agarwal

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Disambiguation of "Agarwal, Anant"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.

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Nivedita Agarwal

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Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.