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Disambiguation of "Iwane, Masahiko"

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An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware.

, , and . ERSA, page 233-239. CSREA Press, (2009)

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Other publications of authors with the same name

Extracting distance from defocused images with different aperture sizes.. Systems and Computers in Japan, 23 (10): 81-91 (1992)An efficient parallel processing using a cache memory with synchronization on a Soc-multiprocessor., and . Circuits, Signals, and Systems, page 142-147. IASTED/ACTA Press, (2005)Organization of Shared Memory with Synchronization for Multiprocessor-on-a-chip., and . ICPADS, page 83-90. IEEE Computer Society, (2002)An intermediate hardware model with load/store unit for C to FPGA., and . FPGA, page 279. ACM, (2009)Tagged communication and synchronization memory for multiprocessor-on-a-chip., , and . Systems and Computers in Japan, 32 (4): 1-13 (2001)Evaluation of mechanisms introduced to improve performance of TSVM cache., and . Parallel and Distributed Computing and Networks, page 502-507. IASTED/ACTA Press, (2004)Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor., and . ISPAN, page 324-333. IEEE Computer Society, (2005)An FPGA implementation of a DWT with 5/3 filter using semi-programmable hardware., , and . APCCAS, page 709-712. IEEE, (2008)An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip., and . ICPADS, page 1-8. IEEE Computer Society, (2007)A Programmable Load/Store Unit on C-based Hardware Design for FPGA., and . FPT, page 361-364. IEEE, (2007)