PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Raghunathan, Anand"

Author of the publication

copydeleteadd this publication to your clipboard
Guest Editors' Introduction: Green Buildings.

, and . IEEE Design & Test of Computers, 29 (4): 5-7 (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Anand Venkatachalam University of Stuttgart

Mahathi Anand University of Stuttgart

 

Other publications of authors with the same name

Hardware Accelerated Power Estimation, , and . CoRR, (2007)STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks., , , and . CoRR, (2014)Variation-Aware System-Level Power Analysis., , , and . IEEE Trans. VLSI Syst., 18 (8): 1173-1184 (2010)Coping with Variations through System-Level Design., , , , , and . VLSI Design, page 581-586. IEEE Computer Society, (2009)Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches., , , and . ISLPED, page 64-69. IEEE, (2013)Computing approximately, and efficiently., , , and . DATE, page 748-751. ACM, (2015)Energy-efficient recognition and mining processor using scalable effort design., , , , and . CICC, page 1-4. IEEE, (2013)Exploiting the forgiving nature of applications for scalable parallel execution., , , and . IPDPS, page 1-12. IEEE, (2010)A framework for efficient and scalable execution of domain-specific templates on GPUs., , and . IPDPS, page 1-12. IEEE, (2009)High-level macro-modeling and estimation techniques for switching activity and power consumption., , and . IEEE Trans. VLSI Syst., 11 (4): 538-557 (2003)