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Improving performance of nested loops on reconfigurable array processors.

, , , and . TACO, 8 (4): 32:1-32:23 (2012)

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Fast graph-based instruction selection for multi-output instructions., , , , , and . Softw., Pract. Exper., 41 (6): 717-736 (2011)A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (7): 1018-1027 (2010)Compiler-managed register file protection for energy-efficient soft error reduction., and . ASP-DAC, page 618-623. IEEE, (2009)Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces., , and . IEEE Trans. VLSI Syst., 24 (8): 2799-2802 (2016)Memory access optimization in compilation for coarse-grained reconfigurable architectures., , , and . ACM Trans. Design Autom. Electr. Syst., 16 (4): 42:1-42:27 (2011)Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (5): 888-897 (2019)Evaluator-executor transformation for efficient pipelining of loops with conditionals., , and . TACO, 10 (4): 62:1-62:23 (2013)Improving performance of nested loops on reconfigurable array processors., , , and . TACO, 8 (4): 32:1-32:23 (2012)RRNet: Repetition-Reduction Network for Energy Efficient Decoder of Depth Estimation., , , and . CoRR, (2019)Improving performance of loops on DIAM-based VLIW architectures., , , and . LCTES, page 135-144. ACM, (2014)