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Fast graph-based instruction selection for multi-output instructions.

, , , , , and . Softw., Pract. Exper., 41 (6): 717-736 (2011)

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A new addressing mode for the encoding space problem on embedded processors., , , , , , , and . SASP, page 58-61. IEEE Computer Society, (2009)Reducing instruction bit-width for low-power VLIW architectures., , , and . ACM Trans. Design Autom. Electr. Syst., 18 (2): 25:1-25:32 (2013)Implementing dynamic implied addressing mode for multi-output instructions., , , , and . CASES, page 87-96. ACM, (2010)Fast graph-based instruction selection for multi-output instructions., , , , , and . Softw., Pract. Exper., 41 (6): 717-736 (2011)Two versions of architectures for dynamic implied addressing mode., , , , and . Journal of Systems Architecture - Embedded Systems Design, 56 (8): 368-383 (2010)Iterative Algorithm for Compound Instruction Selection with Register Coalescing., , , , and . DSD, page 513-520. IEEE Computer Society, (2009)Fast dynamic execution offloading for efficient mobile cloud computing., , , , , , and . PerCom, page 20-28. IEEE Computer Society, (2013)Dynamic Operands Insertion for VLIW Architecture with a Reduced Bit-width Instruction Set., , , , and . IPDPS, page 119-130. IEEE Computer Society, (2012)Orthogonal Instruction Encoding for a 16-bit Embedded Processor with Dynamic Implied Addressing Mode., , , , and . HPCC, page 545-550. IEEE, (2009)A spill data aware memory assignment technique for improving power consumption of multimedia memory systems., and . Multimedia Tools Appl., 78 (5): 5463-5478 (2019)