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Disambiguation of "Kotásek, Zdenek"

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Checker Design for On-line Testing of Xilinx FPGA Communication Protocols.

, , and . DFT, page 152-160. IEEE Computer Society, (2007)

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Testability analysis based on the identification of testable blocks with predefined properties., , and . Microprocessors and Microsystems - Embedded Hardware Design, 32 (5-6): 296-302 (2008)The Identification of registers in RTL Structures for the Test Application., , and . ISoLA (Preliminary proceedings), volume TR-2004-6 of Technical Report, page 317-319. Department of Computer Science, University of Cyprus, (2004)Automated Functional Verification of Application Specific Instruction-set Processors., , , and . IESS, volume 403 of IFIP Advances in Information and Communication Technology, page 128-138. Springer, (2013)Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA., and . DDECS, page 171-174. IEEE Computer Society, (2014)Evolution of synthetic RTL benchmark circuits with predefined testability., , and . ACM Trans. Design Autom. Electr. Syst., 13 (3): 54:1-54:21 (2008)Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis., , and . EWDTS, page 1-7. IEEE, (2018)Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study., , , , , and . DSD, page 597-600. IEEE, (2019)pecial CAI Section Devoted to MEMICS '11: Preface., , , , and . Comput. Informatics, 31 (3): 481- (2012)High Availability Fault Tolerant Architectures Implemented into FPGAs., and . DSD, page 108-115. IEEE Computer Society, (2009)The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption., , and . DSD, page 644-651. IEEE Computer Society, (2010)