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Disambiguation of "Podivinsky, Jakub"

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Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study.

, , , , , and . DSD, page 597-600. IEEE, (2019)

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Jakub Bronik University of Stuttgart

Jakub Wieremiejczuk University of Stuttgart

 

Other publications of authors with the same name

Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis., , and . EWDTS, page 1-7. IEEE, (2018)Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study., , , , , and . DSD, page 597-600. IEEE, (2019)Software Fault Tolerance: The Evaluation by Functional Verification., , and . DSD, page 284-287. IEEE Computer Society, (2015)Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation., , , and . EWDTS, page 1-6. IEEE, (2018)The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications., , , and . DSD, page 312-319. IEEE Computer Society, (2014)Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems., , , and . DSD, page 487-494. IEEE Computer Society, (2016)FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation., , , , and . DSD, page 244-251. IEEE Computer Society, (2018)Program Generation Through a Probabilistic Constrained Grammar., , and . DSD, page 214-220. IEEE Computer Society, (2018)Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller., , and . LATS, page 1-4. IEEE, (2019)FPGA Prototyping and Accelerated Verification of ASIPs., , , and . DDECS, page 145-148. IEEE Computer Society, (2015)