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Checker Design for On-line Testing of Xilinx FPGA Communication Protocols.

, , and . DFT, page 152-160. IEEE Computer Society, (2007)

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High Availability Fault Tolerant Architectures Implemented into FPGAs., and . DSD, page 108-115. IEEE Computer Society, (2009)Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA., , , and . DSD, page 250-257. IEEE Computer Society, (2012)Checker Design for On-line Testing of Xilinx FPGA Communication Protocols., , and . DFT, page 152-160. IEEE Computer Society, (2007)Digital Systems Architectures Based on On-line Checkers., , and . DSD, page 81-87. IEEE Computer Society, (2008)Software system design for solution of effective material layout for the needs of production and logistics., and . Wirel. Networks, 28 (2): 873-882 (2022)SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems., , and . DSD, page 223-230. IEEE Computer Society, (2011)Methodology for Fault Tolerant System Design Based on FPGA into Limited Redundant Area., , and . DSD, page 227-234. IEEE Computer Society, (2013)Fault tolerant CAN bus control system implemented into FPGA., , , and . DDECS, page 289-292. IEEE Computer Society, (2013)Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs., , and . DDECS, page 173-176. IEEE Computer Society, (2010)Test platform for fault tolerant systems design properties verification., , , and . DDECS, page 336-341. IEEE, (2012)