PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Kotásek, Zdenek"

Author of the publication

copydeleteadd this publication to your clipboard
Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs.

, , and . DDECS, page 173-176. IEEE Computer Society, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Kotásek, Zdenek
add a person with the name Kotásek, Zdenek
 

Other publications of authors with the same name

Testability analysis based on the identification of testable blocks with predefined properties., , and . Microprocessors and Microsystems - Embedded Hardware Design, 32 (5-6): 296-302 (2008)Automated Functional Verification of Application Specific Instruction-set Processors., , , and . IESS, volume 403 of IFIP Advances in Information and Communication Technology, page 128-138. Springer, (2013)Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA., and . DDECS, page 171-174. IEEE Computer Society, (2014)The Identification of registers in RTL Structures for the Test Application., , and . ISoLA (Preliminary proceedings), volume TR-2004-6 of Technical Report, page 317-319. Department of Computer Science, University of Cyprus, (2004)Evolution of synthetic RTL benchmark circuits with predefined testability., , and . ACM Trans. Design Autom. Electr. Syst., 13 (3): 54:1-54:21 (2008)Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis., , and . EWDTS, page 1-7. IEEE, (2018)Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study., , , , , and . DSD, page 597-600. IEEE, (2019)pecial CAI Section Devoted to MEMICS '11: Preface., , , , and . Comput. Informatics, 31 (3): 481- (2012)Software Fault Tolerance: The Evaluation by Functional Verification., , and . DSD, page 284-287. IEEE Computer Society, (2015)The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption., , and . DSD, page 644-651. IEEE Computer Society, (2010)