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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

Y. Zhang, C. Zhang, J. Nan, Z. Zhang, X. Zhang, J. Klein, D. Ravelosona, G. Sun, and W. Zhao. IEEE Trans. on Circuits and Systems, 63-I (5): 629-638 (2016)

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Jiachen Zhao University of Stuttgart

Jianyu Zhao University of Stuttgart

Zhibin Zhao University of Stuttgart

Other publications of authors with the same name

Design and analysis of the reference cells for STT-MRAM.L. Zhang, W. Zhao, Y. Zhuang, J. Bao, H. Tang, C. Li, and X. Xiang. IEICE Electronic Express, 10 (12): 20130352 (2013)On restricted edge-connectivity of lexicographic product graphs.W. Zhao, and J. Ou. Int. J. Comput. Math., 91 (8): 1618-1626 (2014)Read disturbance issue for nanoscale STT-MRAM.Y. Ran, W. Kang, Y. Zhang, J. Klein, and W. Zhao. NVMSA, page 1-6. IEEE, (2015)Nanocomputing Block based Multi-Context FPGA.W. Zhao, C. Gamrat, and Y. Lhuillier. ERSA, page 297-298. CSREA Press, (2009)Development of a functional model for the Nanoparticle-Organic Memory transistor.O. Bichler, W. Zhao, C. Gamrat, F. Alibart, S. Pleutin, and D. Vuillaume. ISCAS, page 1663-1666. IEEE, (2010)Robust magnetic full-adder with voltage sensing 2T/2MTJ cell.E. Deng, Y. Wang, Z. Wang, J. Klein, B. Dieny, G. Prenat, and W. Zhao. NANOARCH, page 27-32. IEEE Computer Society, (2015)Full-adder circuit design based on all-spin logic device.Q. An, L. Su, J. Klein, S. Beux, I. O'Connor, and W. Zhao. NANOARCH, page 163-168. IEEE Computer Society, (2015)Approximate computing in MOS/spintronic non-volatile full-adder.H. Cai, Y. Wang, L. Naviner, Z. Wang, and W. Zhao. NANOARCH, page 203-208. ACM, (2016)Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM.H. Zhang, W. Kang, T. Pang, W. Lv, Y. Zhang, and W. Zhao. NANOARCH, page 1-6. ACM, (2016)Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.W. Zhao, J. Portal, W. Kang, M. Moreau, Y. Zhang, H. Aziza, J. Klein, Z. Wang, D. Querlioz, D. Deleruyelle and 4 other author(s). J. Parallel Distrib. Comput., 74 (6): 2484-2496 (2014)

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Disambiguation of "Zhao, Weisheng"

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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

Please choose a person to relate this publication to

Jiachen Zhao University of Stuttgart

Jianyu Zhao University of Stuttgart

Zhibin Zhao University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Zhao, Weisheng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

Please choose a person to relate this publication to

Jiachen Zhao University of Stuttgart

Jianyu Zhao University of Stuttgart

Zhibin Zhao University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.