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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

Y. Zhang, C. Zhang, J. Nan, Z. Zhang, X. Zhang, J. Klein, D. Ravelosona, G. Sun, and W. Zhao. IEEE Trans. on Circuits and Systems, 63-I (5): 629-638 (2016)

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High Performance SoC Design Using Magnetic Logic and Memory.W. Zhao, L. Torres, L. Cargnini, R. Brum, Y. Zhang, Y. Guillemenet, G. Sassatelli, Y. Lakys, J. Klein, D. Etiemble and 2 other author(s). VLSI-SoC (Selected Papers), volume 379 of IFIP Advances in Information and Communication Technology, page 10-33. Springer, (2011)Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.N. Romdhane, W. Zhao, Y. Zhang, J. Klein, Z. Wang, and D. Ravelosona. NANOARCH, page 71-76. IEEE Computer Society/ACM, (2014)Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.W. Zhao, J. Portal, W. Kang, M. Moreau, Y. Zhang, H. Aziza, J. Klein, Z. Wang, D. Querlioz, D. Deleruyelle and 4 other author(s). J. Parallel Distrib. Comput., 74 (6): 2484-2496 (2014)Spintronics for low-power computing.Y. Zhang, W. Zhao, J. Klein, W. Kang, D. Querlioz, Y. Zhang, D. Ravelosona, and C. Chappert. DATE, page 1-6. European Design and Automation Association, (2014)Emerging hybrid logic circuits based on non-volatile magnetic memories.W. Zhao, G. Prenat, J. Klein, B. Dieny, C. Chappert, and D. Ravelosona. NEWCAS, page 1-4. IEEE, (2013)Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.Y. Zhang, C. Zhang, J. Nan, Z. Zhang, X. Zhang, J. Klein, D. Ravelosona, G. Sun, and W. Zhao. IEEE Trans. on Circuits and Systems, 63-I (5): 629-638 (2016)One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.W. Kang, W. Zhao, L. Yang, J. Klein, Y. Zhang, and D. Ravelosona. NVMSA, page 1-6. IEEE, (2014)An overview of spin-based integrated circuits.W. Kang, W. Zhao, Z. Wang, J. Klein, Y. Zhang, D. Chabi, Y. Zhang, D. Ravelosona, and C. Chappert. ASP-DAC, page 676-683. IEEE, (2014)Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology.W. Kang, Y. Zhang, Z. Wang, J. Klein, C. Chappert, D. Ravelosona, G. Wang, Y. Zhang, and W. Zhao. JETC, 12 (2): 16:1-16:42 (2015)Failure and reliability analysis of STT-MRAM.W. Zhao, Y. Zhang, T. Devolder, J. Klein, D. Ravelosona, C. Chappert, and P. Mazoyer. Microelectronics Reliability, 52 (9-10): 1848-1852 (2012)

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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.