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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

Y. Zhang, C. Zhang, J. Nan, Z. Zhang, X. Zhang, J. Klein, D. Ravelosona, G. Sun, and W. Zhao. IEEE Trans. on Circuits and Systems, 63-I (5): 629-638 (2016)

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Jacques Aubron University of Stuttgart

Dominic Klein University of Stuttgart

Dr. -Ing. Simon Kleinknecht University of Stuttgart

Univ. -Prof. Dr. rer. nat. Sara Kleindienst University of Stuttgart

Species-specific responses of marine bacteria to environmental perturbationT. Peña-Montenegro, S. Kleindienst, A. Allen, A. Eren, J. Mccrow, J. Sánchez-Calderón, J. Arnold, and S. Joye. ISME communications, 3 (1): 99 (2023)

Kevin Kleinbeck University of Stuttgart

Other publications of authors with the same name

One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.W. Kang, W. Zhao, L. Yang, J. Klein, Y. Zhang, and D. Ravelosona. NVMSA, page 1-6. IEEE, (2014)Robust neural logic block (NLB) based on memristor crossbar array.D. Chabi, W. Zhao, D. Querlioz, and J. Klein. NANOARCH, page 137-143. IEEE Computer Society, (2011)High Density Asynchronous LUT Based on Non-volatile MRAM Technology.S. Chaudhuri, W. Zhao, J. Klein, C. Chappert, and P. Mazoyer. FPL, page 374-379. IEEE Computer Society, (2010)Exploiting the short-term to long-term plasticity transition in memristive nanodevice learning architectures.C. Bennett, S. Barbera, A. Vincent, J. Klein, F. Alibart, and D. Querlioz. IJCNN, page 947-954. IEEE, (2016)A novel circuit design of true random number generator using magnetic tunnel junction.Y. Wang, H. Cai, L. Naviner, J. Klein, J. Yang, and W. Zhao. NANOARCH, page 123-128. ACM, (2016)An overview of spin-based integrated circuits.W. Kang, W. Zhao, Z. Wang, J. Klein, Y. Zhang, D. Chabi, Y. Zhang, D. Ravelosona, and C. Chappert. ASP-DAC, page 676-683. IEEE, (2014)Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology.W. Kang, Y. Zhang, Z. Wang, J. Klein, C. Chappert, D. Ravelosona, G. Wang, Y. Zhang, and W. Zhao. JETC, 12 (2): 16:1-16:42 (2015)Cross-point architecture for spin transfer torque magnetic random access memoryW. Zhao, S. Chaudhuri, C. Accoto, J. Klein, C. Chappert, and P. Mazoyer. CoRR, (2012)Failure and reliability analysis of STT-MRAM.W. Zhao, Y. Zhang, T. Devolder, J. Klein, D. Ravelosona, C. Chappert, and P. Mazoyer. Microelectronics Reliability, 52 (9-10): 1848-1852 (2012)Design considerations and strategies for high-reliable STT-MRAM.W. Zhao, T. Devolder, Y. Lakys, J. Klein, C. Chappert, and P. Mazoyer. Microelectronics Reliability, 51 (9-11): 1454-1458 (2011)

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Disambiguation of "Klein, Jacques-Olivier"

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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

Please choose a person to relate this publication to

Jacques Aubron University of Stuttgart

Dominic Klein University of Stuttgart

Dr. -Ing. Simon Kleinknecht University of Stuttgart

Univ. -Prof. Dr. rer. nat. Sara Kleindienst University of Stuttgart

Kevin Kleinbeck University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Klein, Jacques-Olivier"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

Please choose a person to relate this publication to

Jacques Aubron University of Stuttgart

Dominic Klein University of Stuttgart

Dr. -Ing. Simon Kleinknecht University of Stuttgart

Univ. -Prof. Dr. rer. nat. Sara Kleindienst University of Stuttgart

Kevin Kleinbeck University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.