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Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges.

, , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)

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Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits., , , , , , and . DATE, page 169-174. IEEE, (2016)Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory., , , , , , , , and . ESSDERC, page 118-121. IEEE, (2019)Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges., , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors., , , , , and . IEEE Trans. VLSI Syst., 27 (3): 560-572 (2019)IPCEI subcontracts contributing to 22-FDX Add-On Functionalities at GF., , , , , , , , , and 10 other author(s). ESSDERC, page 74-77. IEEE, (2019)Reconfigurable nanowire electronics - Device principles and circuit prospects., , , , , and . ESSDERC, page 246-251. IEEE, (2013)Exploiting transistor-level reconfiguration to optimize combinational circuits., , , , , , and . DATE, page 338-343. IEEE, (2017)Nano Security : From Nano-Electronics to Secure Systems, , , , , , , , , and 13 other author(s). 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), page 1334-1339. Piscataway, IEEE, (2021)A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs., , , , , , , , , and . DATE, page 605-608. IEEE, (2018)Eliminating Charge Sharing in Clocked Logic Gates on the Device Level Employing Transistors with Multiple Independent Inputs., , , , and . ESSDERC, page 134-137. IEEE, (2019)