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Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators.

X. Liu, M. Mao, B. Liu, B. Li, Y. Wang, H. Jiang, M. Barnell, Q. Wu, J. Yang, H. Li, and Y. Chen. IEEE Trans. on Circuits and Systems, 63-I (5): 617-628 (2016)

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TEMP: thread batch enabled memory partitioning for GPU.M. Mao, W. Wen, X. Liu, J. Hu, D. Wang, Y. Chen, and H. Li. DAC, page 65:1-65:6. ACM, (2016)A heterogeneous computing system with memristor-based neuromorphic accelerators.X. Liu, M. Mao, H. Li, Y. Chen, H. Jiang, J. Yang, Q. Wu, and M. Barnell. HPEC, page 1-6. IEEE, (2014)An efficient STT-RAM-based register file in GPU architectures.X. Liu, M. Mao, X. Bi, H. Li, and Y. Chen. ASP-DAC, page 490-495. IEEE, (2015)Heterogeneous systems with reconfigurable neuromorphic computing accelerators.S. Li, X. Liu, M. Mao, H. Li, Y. Chen, B. Li, and Y. Wang. ISCAS, page 125-128. IEEE, (2016)RENO: a high-efficient reconfigurable neuromorphic computing accelerator design.X. Liu, M. Mao, B. Liu, H. Li, Y. Chen, B. Li, Y. Wang, H. Jiang, M. Barnell, Q. Wu and 1 other author(s). DAC, page 66:1-66:6. ACM, (2015)Prefetching techniques for STT-RAM based last-level cache in CMP systems.M. Mao, G. Sun, Y. Li, A. Jones, and Y. Chen. ASP-DAC, page 67-72. IEEE, (2014)TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.Z. Liu, M. Mao, T. Liu, X. Wang, W. Wen, Y. Chen, H. Li, D. Wang, Y. Pei, and N. Ge. IEEE Trans. on CAD of Integrated Circuits and Systems, 37 (10): 1985-1998 (2018)Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory.M. Mao, W. Wen, Y. Zhang, Y. Chen, and H. Li. DAC, page 196:1-196:6. ACM, (2014)CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.W. Wen, M. Mao, X. Zhu, S. Kang, D. Wang, and Y. Chen. ICCAD, page 1-8. IEEE, (2013)FACRA: Flexible-Core Architecture Chip Resource Abstractor.T. Sun, H. An, Y. Ren, M. Mao, Y. Liu, M. Xu, and Q. Li. PDCAT, page 440-447. IEEE Computer Society, (2010)

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Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators.

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Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators.