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%0 Journal Article
%1 journals/tcad/LiuMLWWCLWPG18
%A Liu, Zihao
%A Mao, Mengjie
%A Liu, Tao
%A Wang, Xue
%A Wen, Wujie
%A Chen, Yiran
%A Li, Hai
%A Wang, Danghui
%A Pei, Yukui
%A Ge, Ning
%D 2018
%J IEEE Trans. on CAD of Integrated Circuits and Systems
%K dblp
%N 10
%P 1985-1998
%T TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.
%U http://dblp.uni-trier.de/db/journals/tcad/tcad37.html#LiuMLWWCLWPG18
%V 37
@article{journals/tcad/LiuMLWWCLWPG18,
added-at = {2019-08-07T00:00:00.000+0200},
author = {Liu, Zihao and Mao, Mengjie and Liu, Tao and Wang, Xue and Wen, Wujie and Chen, Yiran and Li, Hai and Wang, Danghui and Pei, Yukui and Ge, Ning},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/28901786cf11b187aef8914e7de1afc93/dblp},
ee = {https://doi.org/10.1109/TCAD.2017.2783860},
interhash = {1f7cf59863d34657443484cfa93fa390},
intrahash = {8901786cf11b187aef8914e7de1afc93},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
keywords = {dblp},
number = 10,
pages = {1985-1998},
timestamp = {2019-09-27T08:26:54.000+0200},
title = {TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.},
url = {http://dblp.uni-trier.de/db/journals/tcad/tcad37.html#LiuMLWWCLWPG18},
volume = 37,
year = 2018
}
