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A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier.

C. Peng, Y. Tao, W. Lu, Z. Li, X. Ji, J. Yan, and J. Chen. IEICE Electronic Express, 12 (5): 20150102 (2015)

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Hong Chen University of Stuttgart

Yiyin Chen University of Stuttgart

Jun Chen University of Stuttgart

Lu Chen University of Stuttgart

Yingxing Cheng University of Stuttgart

Other publications of authors with the same name

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip.X. Wu, M. Li, Z. Lin, M. Xi, and J. Chen. Sensors, 13 (7): 8771-8785 (2013)Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier.S. Tan, W. Lu, C. Peng, Z. Li, Y. Tao, and J. Chen. Frontiers of IT & EE, 16 (8): 700-706 (2015)A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design.S. Gao, J. Chen, D. Ke, and X. Wu. APCCAS, page 1465-1468. IEEE, (2006)Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier.Z. Li, C. Peng, W. Lu, L. Guan, Y. Tao, X. Ji, and J. Chen. IEICE Electronic Express, 13 (7): 20150951 (2016)Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application.C. Peng, J. Huang, C. Liu, Q. Zhao, S. Xiao, X. Wu, Z. Lin, J. Chen, and X. Zeng. IEEE Trans. VLSI Syst., 27 (2): 407-415 (2019)Computational insight into dengue virus NS2B-NS3 protease inhibition: A combined ligand- and structure-based approach.J. Chen, H. Jiang, F. Li, B. Hu, Y. Wang, M. Wang, J. Wang, and M. Cheng. Computational Biology and Chemistry, (2018)Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique.C. Peng, L. Kong, X. Wu, Z. Lin, H. Xu, J. Chen, and X. Zeng. IEICE Electronic Express, 15 (10): 20180332 (2018)A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination.C. Liu, C. Peng, Z. Lin, X. Wu, Z. Chen, Q. Zhao, X. Li, J. Chen, X. Zeng, and X. Hu. IEICE Electronic Express, 15 (15): 20180604 (2018)An inverter chain with parallel output nodes for eliminating single-event transient pulse.C. Liu, Z. Lin, X. Wu, C. Peng, Q. Zhao, X. Li, J. Chen, X. Zeng, and X. Hu. IEICE Electronic Express, 16 (4): 20181118 (2019)A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier.C. Peng, Y. Tao, W. Lu, Z. Li, X. Ji, J. Yan, and J. Chen. IEICE Electronic Express, 12 (5): 20150102 (2015)

PUMA

Disambiguation of "Chen, Junning"

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A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier.

Please choose a person to relate this publication to

Hong Chen University of Stuttgart

Yiyin Chen University of Stuttgart

Jun Chen University of Stuttgart

Lu Chen University of Stuttgart

Yingxing Cheng University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Chen, Junning"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier.

Please choose a person to relate this publication to

Hong Chen University of Stuttgart

Yiyin Chen University of Stuttgart

Jun Chen University of Stuttgart

Lu Chen University of Stuttgart

Yingxing Cheng University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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APA
Chicago
DIN 1505
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A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier.