Author of the publication

A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS.

, , , , , and . J. Solid-State Circuits, 45 (11): 2312-2320 (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Kanno, Yusuke
add a person with the name Kanno, Yusuke
 

Other publications of authors with the same name

Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA., , and . IEICE Transactions, 100-C (4): 382-390 (2017)Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 42 (1): 74-83 (2007)A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS., , , , , and . J. Solid-State Circuits, 45 (11): 2312-2320 (2010)Comprehensive electrochemical imaging with local redox cycling-based electrochemical chip device for evaluation of three-dimensional culture cells., , , , , and . MHS, page 16-18. IEEE, (2012)A Method for Measuring of RTN by Boosting Word-Line Voltage in 6-Tr-SRAMs., , , and . IEICE Transactions, 97-C (3): 215-221 (2014)In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution., , , , , , , and . J. Solid-State Circuits, 42 (4): 784-789 (2007)Hierarchical power distribution and power management scheme for a single chip mobile processor., , , , , , , , , and 23 other author(s). DAC, page 292-295. ACM, (2006)