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A System for Designing Parallel Processor Arrays.

, , , and . EUROCAST, volume 1333 of Lecture Notes in Computer Science, page 3-12. Springer, (1997)

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Determination of the Processor Functionality in the Design of Processor Arrays., and . ASAP, page 199-208. IEEE Computer Society, (1997)Optimal Software Pipelining Under Register Constraints., and . PDPTA, CSREA Press, (2000)Optimal Software Pipelining with Rational Initiation Interval., and . PDPTA, page 638-643. CSREA Press, (2002)Localization of Data Transfer in Processor Arrays., and . Euro-Par, volume 1685 of Lecture Notes in Computer Science, page 401-408. Springer, (1999)Design of Processor Arrays for Real-Time Applications., and . Euro-Par, volume 1470 of Lecture Notes in Computer Science, page 1018-1028. Springer, (1998)Propagation of I/O-Variables in Massively Parallel Processor Arrays., and . PDP, page 501-509. IEEE Computer Society, (1996)Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling., , and . Interaction between Compilers and Computer Architectures, page 13-21. IEEE Computer Society, (2004)Optimal Loop Scheduling with Register Constraints Using Flow Graphs., , and . ISPAN, page 180-186. IEEE Computer Society, (2004)Optimal Software Pipelining Under Resource Constraints., and . Int. J. Found. Comput. Sci., 12 (6): 697-718 (2001)A Hardware-Software System for Tomographic Reconstruction., , , and . Journal of Circuits, Systems, and Computers, 12 (2): 203- (2003)