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Analyzing path delays for accelerated testing of logic chips.

E. Ray, B. Linder, R. Robertazzi, K. Stawiasz, A. Weger, E. Yashchin, J. Stathis, and P. Song. IRPS, page 6. IEEE, (2015)

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Modeling of risk losses using size-biased data.E. Yashchin. IBM Journal of Research and Development, 51 (3/4): 309-324 (2007)Analyzing path delays for accelerated testing of logic chips.E. Ray, B. Linder, R. Robertazzi, K. Stawiasz, A. Weger, E. Yashchin, J. Stathis, and P. Song. IRPS, page 6. IEEE, (2015)Defining the controlling parameter in constrained discriminative linear transform for supervised speaker adaptation.D. Jiang, D. Kanevsky, E. Yashchin, and Y. Qin. ICASSP, page 4444-4447. IEEE, (2011)Application of three-parameter lognormal distribution in EM data analysis.B. Li, E. Yashchin, C. Christiansen, J. Gill, R. Filippi, and T. Sullivan. Microelectronics Reliability, 46 (12): 2049-2055 (2006)Statistically regulating program behavior via mainstream computing.M. Stephenson, R. Rangan, E. Yashchin, and E. Hensbergen. CGO, page 238-247. ACM, (2010)On the Analysis and Design of CUSUM-Shewhart Control Schemes.E. Yashchin. IBM Journal of Research and Development, 29 (4): 377-391 (1985)Accelerated Monte Carlo for Kullback-Leibler divergence between Gaussian mixture models.J. Chen, J. Hershey, P. Olsen, and E. Yashchin. ICASSP, page 4553-4556. IEEE, (2008)Estimating the efficiency of collaborative problem-solving, with applications to chip design.M. Wisniewski, E. Yashchin, R. Franch, D. Conrady, G. Fiorenza, and I. Noyan. IBM Journal of Research and Development, 47 (1): 77-88 (2003)The physical design of on-chip interconnections.M. Wisniewski, E. Yashchin, R. Franch, D. Conrady, D. Maynard, G. Fiorenza, and I. Noyan. IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (3): 254-276 (2003)Parametric Estimation for Window Censored Recurrence Data.Y. Zhu, E. Yashchin, and J. Hosking. Technometrics, 56 (1): 55-66 (2014)

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Analyzing path delays for accelerated testing of logic chips.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Analyzing path delays for accelerated testing of logic chips.

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Analyzing path delays for accelerated testing of logic chips.