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TETA: transistor-level waveform evaluation for timing analysis.

, , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 21 (5): 605-616 (2002)

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TETA: Transistor-Level Engine for Timing Analysis., and . DAC, page 595-598. ACM Press, (1998)To do or not to do hierarchical timing?, and . ISPD, page 180. ACM, (2013)Statistical static timing analysis: how simple can we get?, , , , , , and . DAC, page 652-657. ACM, (2005)Modeling unbuffered latches for timing analysis., , and . ICCAD, page 254-260. IEEE Computer Society / ACM, (2004)Piecewise Linear Macromodels for Elementary Logic and Fuzzy Circuits., and . ISCAS, page 1718-1721. IEEE, (1993)Performance computation for precharacterized CMOS gates with RC loads., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 15 (5): 544-553 (1996)An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response., , and . DAC, page 611-616. ACM Press, (1996)RC interconnect synthesis-a moment fitting approach., , , and . ICCAD, page 418-425. IEEE Computer Society / ACM, (1994)Expanding the frequency range of AWE via time shifting., , , and . ICCAD, page 935-938. IEEE Computer Society, (2005)Weibull-based analytical waveform model., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (8): 1156-1168 (2005)