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Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology.

, , , and . ITC, page 1-10. IEEE Computer Society, (2006)

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Improved weight assignment for logic switching activity during at-speed test pattern generation., , , , , and . ASP-DAC, page 493-498. IEEE, (2010)Star test: the theory and its applications., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 19 (9): 1052-1064 (2000)A test-application-count based learning technique for test time reduction., , , and . VLSI-DAT, page 1-4. IEEE, (2015)Clock-domain-aware test for improving pattern compression., and . VLSI-DAT, page 1-4. IEEE, (2015)Design rule check on the clock gating logic for testability and beyond., and . ITC, page 1-8. IEEE Computer Society, (2013)Monitoring the delay of long interconnects via distributed TDC., , , and . ITC, page 1-9. IEEE, (2015)Scan-Encoded Test Pattern Generation for BIST., , and . ITC, page 548-556. IEEE Computer Society, (1997)An Efficient and Effective Methodology on the Multiple Fault Diagnosis., , , and . ITC, page 329-338. IEEE Computer Society, (2003)Programmable Leakage Test and Binning for TSVs., , , and . Asian Test Symposium, page 43-48. IEEE Computer Society, (2012)On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs., , , , and . ATS, page 162-167. IEEE Computer Society, (2014)