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Stress-resiliency of AI Implementations on FPGAs

, , , , and . 2023 33rd International Conference on Field-Programmable Logic and Applications (FPL), page 333-338. IEEE, (2023)
DOI: 10.1109/FPL60245.2023.00057

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Stress-resiliency of AI implementations on FPGAs, , , , and . International Conference on Field Programmable Logic and Applications (FPL), (2023)Stress-resiliency of AI Implementations on FPGAs, , , , and . 2023 33rd International Conference on Field-Programmable Logic and Applications (FPL), page 333-338. IEEE, (2023)A mapping algorithm for defect-tolerance of reconfigurable nano-architectures.. ICCAD, page 668-672. IEEE Computer Society, (2005)Aging-aware timing analysis considering combined effects of NBTI and PBTI., , and . ISQED, page 53-59. IEEE, (2013)Stress-aware P/G TSV planning in 3D-ICs., , , and . ASP-DAC, page 94-99. IEEE, (2015)Chip-level modeling and analysis of electrical masking of soft errors., , , and . VTS, page 1-6. IEEE Computer Society, (2013)Defects and Faults in Quantum Cellular Automata at Nano Scale., , , and . VTS, page 291-296. IEEE Computer Society, (2004)Investigation of NBTI and PBTI induced aging in different LUT implementations., , and . FPT, page 1-8. IEEE, (2011)Investigation of aging effects in different implementations and structures of programmable routing resources of FPGAs., , and . FPT, page 215-219. IEEE, (2012)Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation., and . European Test Symposium, page 1-6. IEEE Computer Society, (2012)