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Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications

S. Deng, M. Benkhelifa, S. Thomann, Z. Faris, Z. Zhao, T. Huang, Y. Xu, V. Narayanan, K. Ni, and H. Amrouch. 2022 International Electron Devices Meeting (IEDM), IEEE, (2022)
DOI: 10.1109/IEDM45625.2022.10019400

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An integer linear programming-based tool for wireless sensor networks.I. Kadayif, M. Kandemir, N. Vijaykrishnan, and M. Irwin. J. Parallel Distrib. Comput., 65 (3): 247-260 (2005)Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues.A. Gayasen, N. Vijaykrishnan, M. Kandemir, and A. Rahman. IEEE Trans. VLSI Syst., 16 (7): 882-893 (2008)Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers.T. Ragheb, A. Ricketts, M. Mondal, S. Kirolos, G. Link, V. Narayanan, and Y. Massoud. IEEE Trans. on Circuits and Systems, 56-I (2): 374-383 (2009)Java Runtime Systems: Characterization and Architectural Implications.R. Radhakrishnan, N. Vijaykrishnan, L. John, A. Sivasubramaniam, J. Rubio, and J. Sabarinathan. IEEE Trans. Computers, 50 (2): 131-146 (2001)A compiler-based approach for dynamically managing scratch-pad memories in embedded systems.M. Kandemir, J. Ramanujam, M. Irwin, N. Vijaykrishnan, I. Kadayif, and A. Parikh. IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (2): 243-260 (2004)Using Memory Compression for Energy Reduction in an Embedded Java System.G. Chen, M. Kandemir, N. Vijaykrishnan, M. Irwin, and W. Wolf. Journal of Circuits, Systems, and Computers, 11 (5): 537-556 (2002)Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations.S. Yang, W. Wolf, and N. Vijaykrishnan. IEEE Trans. Computers, 54 (6): 714-726 (2005)Reliability-Aware SOC Voltage Islands Partition and Floorplan.S. Yang, W. Wolf, N. Vijaykrishnan, and Y. Xie. ISVLSI, page 343-348. IEEE Computer Society, (2006)Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach.S. Yang, W. Wolf, N. Vijaykrishnan, D. Serpanos, and Y. Xie. DATE, page 64-69. IEEE Computer Society, (2005)On the Effects of Process Variation in Network-on-Chip Architectures.C. Nicopoulos, S. Srinivasan, A. Yanamandra, D. Park, V. Narayanan, C. Das, and M. Irwin. IEEE Trans. Dependable Sec. Comput., 7 (3): 240-254 (2010)

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Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications

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Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications