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Reliability-Aware SOC Voltage Islands Partition and Floorplan.

S. Yang, W. Wolf, N. Vijaykrishnan, and Y. Xie. ISVLSI, page 343-348. IEEE Computer Society, (2006)

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Yifan Xie University of Stuttgart

Optimal Synthesis of Opacity-Enforcing Supervisors for Qualitative and Quantitative SpecificationsY. Xie, S. Li, and X. Yin. IEEE transactions on automatic control, 69 (8): 4958-4973 (2023)

Yiwen Yuan University of Stuttgart

Other publications of authors with the same name

ProactiveDRAM: A DRAM-initiated retention management scheme.J. Wang, X. Dong, and Y. Xie. ICCD, page 22-27. IEEE Computer Society, (2014)Design Space Exploration for 3-D Cache.Y. Tsai, F. Wang, Y. Xie, N. Vijaykrishnan, and M. Irwin. IEEE Trans. VLSI Syst., 16 (4): 444-455 (2008)Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects.W. Liu, Y. Wang, X. Feng, Y. Huang, H. Yang, Y. Xie, and G. Chen. IEEE Design & Test, 31 (5): 28-35 (2014)Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs.Y. Chen, E. Kursun, D. Motschman, C. Johnson, and Y. Xie. ISLPED, page 397-402. IEEE/ACM, (2011)Power optimization for FinFET-based circuits using genetic algorithms.J. Ouyang, and Y. Xie. SoCC, page 211-214. IEEE, (2008)Designing vertical bandwidth reconfigurable 3D NoCs for many core systems.Q. Zou, J. Zhan, F. Ge, M. Poremba, and Y. Xie. 3DIC, page 1-7. IEEE, (2014)Self-powered wearable sensor node: Challenges and opportunities.Y. Liu, H. Li, X. Li, J. Xue, Y. Xie, and H. Yang. CASES, page 189. IEEE, (2015)Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits.R. Ramanarayanan, V. Degalahal, K. Ramakrishnan, J. Kim, V. Narayanan, Y. Xie, M. Irwin, and K. Unlu. IEEE Trans. Dependable Sec. Comput., 6 (3): 202-216 (2009)Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs.Z. Li, Y. Ma, Q. Zhou, Y. Cai, Y. Xie, and T. Huang. Integration, 46 (1): 1-9 (2013)Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design.Y. Xie, and W. Hung. VLSI Signal Processing, 45 (3): 177-189 (2006)

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Disambiguation of "Xie, Yuan"

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Reliability-Aware SOC Voltage Islands Partition and Floorplan.

Please choose a person to relate this publication to

Yifan Xie University of Stuttgart

Yiwen Yuan University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Xie, Yuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Reliability-Aware SOC Voltage Islands Partition and Floorplan.

Please choose a person to relate this publication to

Yifan Xie University of Stuttgart

Yiwen Yuan University of Stuttgart

Other publications of authors with the same name

Disambiguation

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DOI
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Reliability-Aware SOC Voltage Islands Partition and Floorplan.