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Functional enhancements of TMR for power efficient and error resilient ASIC designs.

, , , , , and . DDECS, page 183-188. IEEE Computer Society, (2011)

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On the Impact of Caching for High Performance Packet Classifiers., , and . GLOBECOM, page 2314-2318. IEEE, (2008)Modeling temperature distribution in Networks-on-Chip using RC-circuits., , , and . DDECS, page 229-232. IEEE Computer Society, (2010)Monitoring and Control of Temperature in Networks-on-Chip., , , and . MEMICS, volume 16 of OASIcs, page 124-131. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany, (2010)Rapid Evolution of Time-Efficient Packet Classifiers., , and . IEEE Congress on Evolutionary Computation, page 2793-2799. IEEE, (2006)Functional enhancements of TMR for power efficient and error resilient ASIC designs., , , , , and . DDECS, page 183-188. IEEE Computer Society, (2011)Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown., , , , and . DDECS, page 12-15. IEEE, (2012)Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown., , , , and . SBCCI, ACM, (2009)System level modeling of Networks-on-Chip for power estimation and design space exploration., , , , and . MBMV, page 25-34. Institut für Angewandte Mikroelektronik und Datentechnik, Fakultät für Informatik und Elektrotechnik, Universität Rostock, (2013)Accelerating the Evolution of Evolvable Hardware-based Packet Classifiers., , , and . WEAH, page 27-34. IEEE, (2007)