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Disambiguation of "Nane, Razvan"

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Controlling a complete hardware synthesis toolchain with LARA aspects.

, , , , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (8-C): 1073-1089 (2013)

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Other publications of authors with the same name

IP-XACT extensions for Reconfigurable Computing., , , , , and . ASAP, page 215-218. IEEE Computer Society, (2011)Controlling a complete hardware synthesis toolchain with LARA aspects., , , , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (8-C): 1073-1089 (2013)Quipu: A Statistical Model for Predicting Hardware Resources., , , , , and . TRETS, 6 (1): 3:1-3:25 (2013)An Image Processing VLIW Architecture for Real-Time Depth Detection., , , , and . SBAC-PAD, page 158-165. IEEE Computer Society, (2016)Deriving Resource Efficient Designs Using the REFLECT Aspect-Oriented Approach - (Extended Abstract)., , , , , , , and . ARC, volume 7806 of Lecture Notes in Computer Science, page 226-228. Springer, (2013)High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain., , , , and . EUC, page 138-145. IEEE Computer Society, (2014)Computation-in-memory based parallel adder., , , , , and . NANOARCH, page 57-62. IEEE Computer Society, (2015)A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons., , and . ACM Great Lakes Symposium on VLSI, page 71-76. ACM, (2017)Area constraint propagation in high level synthesis., , and . FPT, page 247-252. IEEE, (2012)Skeleton-based design and simulation flow for Computation-in-Memory architectures., , , , , and . NANOARCH, page 165-170. ACM, (2016)