Author of the publication

Controlling a complete hardware synthesis toolchain with LARA aspects.

, , , , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (8-C): 1073-1089 (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Optimising and adapting high-level hardware designs., and . FPT, page 150-157. IEEE, (2002)Mapping and scheduling with task clustering for heterogeneous computing systems., , , and . FPL, page 275-280. IEEE, (2008)Power-Aware and Branch-Aware Word-Length Optimization., , , and . FCCM, page 129-138. IEEE Computer Society, (2008)HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms., , , , , , , , , and 1 other author(s). IEEE Micro, 30 (5): 88-97 (2010)Reconfigurable design with clock gating., , , and . ICSAMOS, page 187-194. IEEE, (2008)Specifying Compiler Strategies for FPGA-based Systems., , , , , , and . FCCM, page 192-199. IEEE Computer Society, (2012)HARNESS Project: Managing Heterogeneous Computing Resources for a Cloud Platform., , , , , , , and . ARC, volume 8405 of Lecture Notes in Computer Science, page 324-329. Springer, (2014)Performance Estimation for Exascale Reconfigurable Dataflow Platforms., , , , , and . FPT, page 314-317. IEEE, (2018)High performance in the cloud with FPGA groups., , , , and . UCC, page 1-10. ACM, (2016)Relation-oriented resource allocation for multi-accelerator systems., , , , , , , , and . ASAP, page 243-244. IEEE Computer Society, (2016)