Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Chrzanowska-Jeske, Malgorzata
add a person with the name Chrzanowska-Jeske, Malgorzata
 

Other publications of authors with the same name

Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes., , and . ICECS, page 774-777. IEEE, (2014)Board-level multiterminal net assignment for the partial cross-bar architecture., , , , , and . IEEE Trans. VLSI Syst., 11 (3): 511-514 (2003)Generating random benchmark circuits for floorplanning., and . ISCAS (5), page 345-348. IEEE, (2004)Floorplanning with performance-based clustering., , and . ISCAS (4), page 724-727. IEEE, (2003)A global approach to the variable ordering problem in PSBDDs., and . ISCAS (5), page 117-120. IEEE, (2001)Modeling of substrate noise block properties for early prediction., and . ISCAS (3), page 3015-3018. IEEE, (2005)Regular symmetric arrays for non-symmetric functions.. ISCAS (1), page 391-394. IEEE, (1999)Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs., , and . VLSI Design, 2002 (1): 13-21 (2002)Substrate noise modeling in early floorplanning of MS-SOCs., , , and . ASP-DAC, page 819-823. ACM Press, (2005)Buffered Interconnects in 3D IC Layout Design., , and . SLIP, page 4:1-4:8. ACM, (2016)