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Multi-ghz Sige Bicmos Fpgas with New Architecture and Novel Power Management Techniques.

, , , , , , , and . Journal of Circuits, Systems, and Computers, 14 (2): 179-194 (2005)

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Carry Chains for Ultra High-Speed SiGe HBT Adders., , , , , , and . IEEE Trans. on Circuits and Systems, 58-I (9): 2201-2210 (2011)Design of BiCMOS SRAMs for high-speed SiGe applications., , , , , , , , and . IET Circuits, Devices & Systems, 8 (6): 487-498 (2014)Predicting the Performance of a 3D Processor-Memory Chip Stack., , , , , and . IEEE Design & Test of Computers, 22 (6): 540-547 (2005)52 Gb/s 16: 1 transmitter in 0.13 μm SiGe BiCMOS technology., , , , and . IET Circuits, Devices & Systems, 1 (6): 427-432 (2007)A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme., , , , , , , , and . FPGA, page 248. ACM, (2003)The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA., , , , , , , , and . ACM Great Lakes Symposium on VLSI, page 141-144. ACM, (2004)Multi-ghz Sige Bicmos Fpgas with New Architecture and Novel Power Management Techniques., , , , , , , and . Journal of Circuits, Systems, and Computers, 14 (2): 179-194 (2005)A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration., , , , , and . IEEE Trans. VLSI Syst., 18 (6): 967-977 (2010)A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC., , , , , , , , and . Integration, 38 (3): 525-540 (2005)140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology., , , , , and . J. Solid-State Circuits, 50 (11): 2703-2713 (2015)