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A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices., , , , , , , , and . IRPS, page 1-5. IEEE, (2019)Automated Massive RTN Characterization Using a Transistor Array Chip., , , , , , , , and . SMACD, page 29-32. IEEE, (2018)A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation., , , , , , , , and . SMACD, page 53-56. IEEE, (2018)A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging., , , , , , , , , and . SMACD, page 1-4. IEEE, (2017)TARS: A toolbox for statistical reliability modeling of CMOS devices., , , , , , and . SMACD, page 1-4. IEEE, (2017)Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models., , , , , , , , , and 2 other author(s). SMACD, page 73-76. IEEE, (2018)New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors., , , , , , , and . DATE, page 150-155. IEEE, (2019)TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level., , , , , , , and . SMACD, page 197-200. IEEE, (2019)A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI., , , , , , , , , and . J. Solid-State Circuits, 54 (2): 476-488 (2019)Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability., , , , , , , , , and . IRPS, page 6-1. IEEE, (2018)