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Disambiguation of "Kawaguchi, Hiroshi"

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Bit error rate estimation in SRAM considering temperature fluctuation.

, , , , , , , and . ISQED, page 516-519. IEEE, (2012)

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Other publications of authors with the same name

A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system., , , and . FPT, page 341-344. IEEE, (2008)Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection., , , , , and . SiPS, page 197-202. IEEE, (2012)A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction., , , , , , and . ISQED, page 489-492. IEEE, (2012)Quality of a Bit (QoB): A New Concept in Dependable SRAM., , , , , , and . ISQED, page 98-102. IEEE Computer Society, (2008)An accurate soft error propagation analysis technique considering temporal masking disablement., , , , , and . IOLTS, page 23-25. IEEE, (2015)A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM., , , , , , , and . ARCS Workshops, page 1-5. VDE Verlag / IEEE Xplore, (2014)A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor., , , , , , , , , and . CICC, page 1-4. IEEE, (2015)Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential., , , , , , and . IPSJ Trans. System LSI Design Methodology, (2011)Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs., , , , and . IEEE Trans. VLSI Syst., 14 (4): 430-435 (2006)A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor., , , , , , and . IEICE Transactions, 99-C (8): 901-908 (2016)